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bright bm29f400t/bm29f400b m icro electronics inc. 4megabit (512k 8/ 256k 16) 5volt sector erase c mos flash memory a winbond company publication release date: december 1999 - 1 - revision a2 general description the bm29f400 is an 4 megabit, 5.0 volt - only cmos flash memory device organized as a 512 kbytes of 8 - bits each, or 256 kbytes of 16 bits each. the device is offered in standard 48 - pin tsop package. it is designed to be programmed and era sed in - system with a 5.0 volt power - supply and can also be reprogrammed in standard eprom programmers. with access times of 90 ns, 120 ns, and 150 ns, the bm29f400 has separate chip enable ce , write enable we , and output enable oe controls. bmi's memory devices reliably store memory data even after 100,000 program and erase cycles. the bm29f400 is entirely pin and command set compatible with the jedec standard for 4 megabit flash memory devices. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state - machine which controls the erase and programming circuitry. write cycles also internally latch addresses and da ta needed for the programming and erase operations. the bm29f400 is programmed by executing the program command sequence. this will start the internal byte/word programming algorithm that automatically times the program pulse width and also verifies the pr oper cell margin. erase is accomplished by executing either the sector erase or chip erase command sequence. this will start the internal erasing algorithm that automatically times the erase pulse width and also verifies the proper cell margin. no preprogr amming is required prior to execution of the internal erase algorithm. sectors of the bm29f400 flash memory array are electrically erased via fowler - nordheim tunneling. bytes/words are programmed one byte/word at a time using a hot electron injection mecha nism. the bm29f400 features a sector erase architecture. the device memory array is divided into one 16 kbytes, two 8 kbytes, one 32 kbytes, and seven 64 kbytes. sectors can be erased individually or in groups without affecting the data in other sectors. m ultiple sector erase and full chip erase capabilities add flexibility to altering the data in the device. to protect this data from accidental program and erase, the device also has a sector protect function. this function hardware write protects the selec ted sector(s). the sector protect and sector unprotect features can be enabled in a prom programmer. for read, program and erase operation, the bm29f400 needs a single 5.0 volt power - supply. internally generated and well regulated voltages are provided for the program and erase operation. a low vcc detector inhibits write operations on loss of power. end of program or erase is detected by the ready/busy status pin, data polling of dq7, or by the toggle bit i feature on dq6. once the program or erase cycle h as been successfully completed, the device internally resets to the read mode. the bm29f400 also has a hardware reset pin. driving the reset pin low during execution of an internal programming or erase command will termi nate the operation and reset the device to the read mode. the reset pin may be tied to the system reset circuitry, so that the system will have access to boot code upon completion of system reset, even if the flash device is in the proces s of an internal programming or erase operation. if the device is reset using the reset pin during an internal programming or erase operation, data in the address locations on which the internal state
bright bm29f400t/bm29f400b m icroelectronics inc. - 2 - machine is operating will be erroneou s. thus, these address locations will need rewriting after the device is reset. features 5.0v +/ - 10% program and erase - minimizes system - level power requirements high performance - 90 ns access time compatible with jedec - standard commands - uses software commands, pinouts, and packages following industry standards for single power supply flash memory typically 100,000 program/erase cycles sector erase architecture - one 16 kbytes, two 8 kbytes, one 32 kbytes, and seven 64 kbytes - any combination of sectors can be erased concurrently; also supports full chip erase erase suspend/resume - suspend a sector erase operation to allow a data read in a sector not being erased within the same device ready/busy - ry/by output pin for detection of programming or erase cycle completion reset - hardware pin resets the internal state machine to the read mode internal erase algorithms - automatically erases a sector, any combination of sectors, or the entire chip internal programming algorithms - automatically program s and verifies data at a specified address low power consumption - 20 ma typical active read current for byte mode - 28 ma typical active read current for word mode - 30 ma typical write/erase current sector protection - hardware method disables any combination of sectors from a program or erase operation boot code sector architecture family part no. - 90 - 120 - 150 maximum access time (ns) 90 120 150 ce (e) access time (ns) 90 120 150 oe (g) access time (ns) 35 50 60 *this speed is available with vcc = 5v +/ - 5% variation
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 3 - revision a2 pin configurations a15 a14 a13 a12 a11 a10 a9 a8 nc nc we reset nc nc ry/by nc a17 a7 a6 a5 a4 a3 a2 a1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 byte vss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe vss ce a0 standard tsop pin description a0 - a17 address inputs dq0 - dq14 data input/output dq15/a - 1 data input/output, ad dress max. ce chip enable oe output enable we write enable v ss device ground reset hardware reset pin, active low ry/by ready/busy status output v cc device power supply byte selects 8 - bit or 16 - bit mode nc not internally connected block diagram vcc vss ry/by buffer state control command register vcc detector timer pgm voltage generator erase boltage generator chip enable output enable logic input/output buffers data latch y-gating cell matrix x-decoder y-decodor address latch stb stb a0-a16 a-1 /oe /ce /we /byte /reset dq0-dq15
bright bm29f400t/bm29f400b m icroelec tronics inc. - 4 - bus operation table 1. bus operations ( byte = v ih ) (1) operation ce oe we a0 a1 a6 a9 dq0 - dq15 reset electronic id manufacturer (2) l l h l l l v id code h electronic id device (2) l l h h l l v id code h read (3) l l h a0 a1 a6 a9 d out h standby h x x x x x x high z h har dware reset x x x x x x x high z l output disable l h h x x x x high z x write l h l a0 a1 a6 a9 d in (4) h verify sector protect (2) l l h l h l v id code h temporary sector unprotect x x x x x x x x v id notes: 1. l = v il , h = v ih , x = don't care. see dc characteristics for voltage levels. 2. manufacturer and device codes may also be accessed via a command register sequence. refer to table 6. 3. we can be v il if ce is v il , oe at v ih initiates the write operations. 4. refer to table 6 for valid d in during a write operation. table 2. bus operations ( byte = v il ) (1) operation ce oe we a0 a1 a6 a9 dq0 - dq7 dq8 - dq15 reset electronic id manufacturer (2) l l h l l l v id code high z h electronic id device (2) l l h h l l v id code high z h read (3) l l h a0 a1 a6 a9 d out high z h standby h x x x x x x high z high z h hardware reset x x x x x x x high z hi gh z l output disable l h h x x x x high z high z h write l h l a0 a1 a6 a9 d in (4) high z h verify sector protect (2) l l h l h l v id code high z h temporary sector unprotect x x x x x x x x high z v id notes: 1. l = v il , h = v ih , x = don't care. see d c characteristics for voltage levels. 2. manufacturer and device codes may also be accessed via a command register sequence. refer to table 6. 3. we can be v il if ce is v il , oe at v ih initiates the write operations. 4. refer to table 6 for valid d in during a write operation.
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 5 - revision a2 table 3. sector protection verify electronic id codes type a17 - a12 a6 a1 a0 code (hex) manufacturer code x v il v il v il adh 29f400t byte x v il v il v ih 23h 29f400 word 22,23h 29f400b byte x v il v il v ih abh word 22 abh sector protection sector address v il v ih v il 01h(1) note: outputs 01h at protected sector addresses, and outputs 00h at unprotected addresses. table 4. sector address tables (bm29f400t) a17 a 16 a15 a14 a13 a12 (x8) address range (x16) address range sa0 0 0 0 x x x 00000h - 0ffffh 00000h - 07fffh sa1 0 0 1 x x x 10000h - 1ffffh 08000h - 0ffffh sa2 0 1 0 x x x 20000h - 2ffffh 10000h - 17fffh sa3 0 1 1 x x x 30000h - 3ffffh 18000h - 1ffffh sa4 1 0 0 x x x 4 0000h - 4ffffh 20000h - 27fffh sa5 1 0 1 x x x 50000h - 5ffffh 28000h - 2ffffh sa6 1 1 0 x x x 60000h - 6ffffh 30000h - 37fffh sa7 1 1 1 0 x x 70000h - 77fffh 38000h - 3bfffh sa8 1 1 1 1 0 0 78000h - 79fffh 3c000h - 3cfffh sa9 1 1 1 1 0 1 7a000h - 7bfffh 3d000h - 3dfffh sa1 0 1 1 1 1 1 x 7c000h - 7ffffh 3e000h - 3ffffh notes: 1. the address range is a17:a - 1 if in byte mode ( byte = v il ). 2. the address range is a17:a0, if in word mode ( byte = v ih ). table 5. sector address tables (bm29f400b) a17 a16 a15 a14 a13 a12 (x8) address range x16) address range sa0 0 0 0 0 0 x 00000h - 03fffh 00000h - 01fffh sa1 0 0 0 0 1 0 04000h - 05fffh 02000h - 02fffh sa2 0 0 0 0 1 1 06000h - 07fffh 03000h - 03fffh sa3 0 0 0 1 x x 08000h - 0ffffh 04000h - 07fffh sa4 0 0 1 x x x 10000h - 1ffffh 08000h - 0ffffh sa5 0 1 0 x x x 20000h - 2ffffh 10000h - 17fffh sa6 0 1 1 x x x 30000h - 3ffffh 18000h - 1ffffh sa7 1 0 0 x x x 40000h - 4ffffh 20000h - 27fffh sa8 1 0 1 x x x 50000h - 5ffffh 28000 h - 2ffffh sa9 1 1 0 x x x 60000h - 6ffffh 30000h - 37fffh sa10 1 1 1 x x x 70000h - 7ffffh 38000h - 3ffffh notes: 1. the address range is a17:a - 1 if in byte mode ( byte = v il ). 2. the address range is a17:a0, if in word mode ( byte = v ih ).
bright bm29f400t/bm29f400b m icroelec tronics inc. - 6 - electronic id mode the electronic id mode allows the reading out of a binary code from the device and will identify its manufacturer and device type. this mode is intended for use by programming equipment for the p urpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5v to 12 .5v) on address pin a9. two identifier bytes may then be sequenced from the device outputs by toggling address a0 from v il to v ih . all addresses are don't cares except a0, a1, and a6 (see table 3). manufacturer and device codes may also be read via the com mand register; for instance, when the bm29f400 is erased or programmed in a system without access to high voltage on the a9 pin. the command sequence is illustrated in table 6 (refer to electronic id command section). byte 0 (a0 = v il ) represents the manuf acturer's code (bright microelectronics = adh) and byte 1 (a0 = v ih ) the device identifier code (bm29f400t = 23h and bm29f400b = abh for 8 - bit mode; bm29f400t = 2223h and bm29f400b = 22abh for 16 - bit mode). these two byte words are given in table 3. to rea d the proper device codes when executing the electronic id, all identifiers for manufacturer and device will exhibit odd parity with the msb (dq7) defined as the parity bit. a1 must be v il (see table 3). read mode the bm29f400 has three con trol functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. as shown in table 1, we should be held at v ih , except in write mode and enable sector protect mode. address access time (t acc ) is equal to the delay from stable addresses to valid output data. chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. output enable access time is the delay from the falling edge of oe to valid data at the output pins (assuming th e addresses have been stable for at least t acc - t oe time). standby mode and hardware reset standby mode the bm29f400 has two methods for implementing standby mode. the first method requi res use of both the ce pin and the reset pin. the second method only requires use of the reset pin. when using both pins, a cmos standby mode is achieved when both ce and reset are held at vcc 0.5v. in this condition, the current consumed is typically less than 100 m a. a ttl standby mode is achieved with both ce and reset held at v ih . in this condition, the typical current required is reduced to 200 m a. the device can be read with standard access time (t ce ) from either of these two standby modes. when using the reset pin only, a cmos standby mode is achieved with reset held at v ss 0.5v. i n this condition, the current consumed is typically less than 100 m a. a ttl standby mode is achieved with reset held at v il . in this condition, the typical current required is reduced to 1 ma. once the reset pin is taken high, the device requires 500 ns of wake - up time before outputs are valid for a read access.
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 7 - revision a2 if the device is deselected during programming or erase, the device will draw active current until the programming or erase operation is completed. in the standby mode the outputs are in a high impedance state, independent of the oe input. output disable mode with the oe input at a logic high level (v ih ), output from the device is disabled. this wi ll cause the output pins to be in a high impedance state. it is shown in table 1 that ce = v il and we = v ih for output disable. this is to differentiate output disable mode from write mode and to prevent inadverten t writes during output disable. program and erase modes device programming and erase are accomplished via the command register. contents of the register serve as inputs to the internal state machine. outputs of the state machi ne dictate the function of the device. the command register itself does not occupy any addressable memory locations. the register is a latch used to store the commands along with the addresses and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happe ns later, while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac characteristics for programming/erase and their respective timing waveforms for specific timing parameters. enable sector protect and verify sector protect modes the bm29f400 has a hardware sector protect mode that disables both programming and erase operation to the protected sector(s). there are total of 11 sectors in this device. the sector protect feature is enabled using the programming equipment at the user's site. the device is shipped from the bmi factory with all sectors unprotected. to verify programmi ng of the protection circuitry, the programming equipment must force v id on the address pin a9 with ce and oe at v il and we at v ih . as shown in table 2, scanning the sector addresses while (a6, a1 and a0) = (0, 1, 0) will produce a 01h code at the device output pins for a protected sector. in the verify sector protect mode, the device will read 00h for an unprotected sector. in this mode, the lower order addresses, except for a0, a1 and a6, are don't care. address locations with a1 = v il are reserved for electronic id manufacturer and device codes. it is also possible to determine if a sector is protected in - system by writing the electronic id command (described in the electronic id command secti on below.) temporary sector unprotect mode the bm29f400 has a temporary sector unprotect feature that allows the protect feature to be temporarily suspended to change data in a protected sector in - system. the temporary sector unprotect mode is activated by setting the reset pin to v id (11.5v - 12.5v). in this mode, protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset pin, a ll previously protected sectors will be protected. refer to the temporary sector unprotect algorithm and timing waveforms.
bright bm29f400t/bm29f400b m icroelec tronics inc. - 8 - read reset command the read or reset operation is initiated by writing the read/reset command sequence in to the command register. microprocessor read cycles retrieve the data from the memory. the device remains enable for reads until the command register contents are changed. the device will automatically power - up in the rea d/reset mode. in this case, a command sequence is not needed to read the memory data. this default power - up to read mode ensures that no spurious changes of the data can take place during the power transitions. refer to the ac characteristics for read - only operation and the respective timing waveforms for the specific timing parameters. electronic id command the bm29f400 contains an electronic id command to supplement the traditional prom programming method described in the elec tronic id mode section. the operation is initiated by writing the electronic id command sequence into the command register. following command write, a read cycle from address xx00h retrieves manufacturer code of adh. a read cycle from address xx01h returns the device code (bm29f400t = 23h and bm29f400b = abh for 8 - bit mode; bm29f400t = 2223h and bm29f400b = 22abh for 16 - bit mode) (see table 3). all manufacturer and device codes exhibit odd parity with the msb (dq7) defined as the parity bit. the electronic id command can also be used to identify protected sectors. after writing the electronic id command sequence, the cpu can scan the sector addresses (see table 4 and table 5) while (a6, a1, a0) = (0, 1, 0). protected sectors will return 01h on the data outpu ts and unprotected sectors will return 00h. to terminate the operation, it is necessary to write the read/reset command sequence into the command register. byte/word programming command the device is programmed on a by te - by - byte (or word - by - word) basis. programming is a four bus cycle operation (see table 6). there are two "unlock" write cycles. these are followed by the program set - up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later, and program data (pd) is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we , whichever happens first, begins programming using the embedded program algorithm. upon executing the algorithm, the system is not required to provide further controls or timings. the device will automatically provide adequate internally gene rated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on dq7 (also used as data polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see table 7, write operation status flags). therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for data po lling operations. data polling must be performed at the memory location which is being programmed. any commands written to the chip during the internal program algorithm will be ignored. if a hardware reset occurs durin g the programming operation, the data at that particular location will be corrupted.
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 9 - revision a2 byte/word programming is allowed in any sequence, and across sector boundaries. however, remember that a data "0" cannot be programmed to a data "1". only erase operations can convert a logical "0" to a logical "1". attempting to program data from "0" to "1" may cause the device to exceed time limits, or even worse, result in an apparent success according to the data polling algorithm. in the later case, however, a subsequent read of this bit will show that the data is still a logical "0". figure 1 illustrates the byte/word programming algorithm using typical command strings and bus operations. the device will ignore any commands written to the chip durin g execution of the internal byte/word programming algorithm. if a hardware reset occurs during the byte/word programming operation, the data at that particular address location will be corrupted. chip erase command chip erase is a six bus cycle operation (see table 6). the chip erase begins on the rising edge of the last we pulse in the command sequence. upon executing the chip erase command sequence, the device's internal state machine execu tes an internal erase algorithm. the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated erase pulses and verify chip erase within the proper cell margins. during chip erase, al l sectors of the device are erased except protected sectors. during chip erase, data bit dq7 shows a logical "0". this operation is known as data polling. the erase operation is completed when the data on dq7 is a logical "1" (see write operation status section). upon completion of the chip erase operation, the device returns to read mode. at this time, the address pins are no longer latched. note that data polling must be performed at a sector address within any of the sectors being erased and not a protected sector to ensure that dq7 returns a logical "1" upon completion of the chip erase operation. figure 2 illustrates the chip erase algorithm using typical command strings and bus operations. the device will ignore an y commands written to the chip during execution of the internal chip erase algorithm. if a hardware reset occurs during the chip erase operation, the data in the device will be corrupted. sector erase command s ector erase is a six bus cycle operation (see table 6). the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command data is latched on the rising edge of we . an internal device timer will initiate the sector erase operation 100 m s 20% (80 m s to 120 m s) from the rising edge of the we pulse for the last sector erase command entered on the device. upon executing the sector erase comma nd sequence, the device's internal state machine executes an internal erase algorithm. the system is not required to provide further controls or timings. the device automatically provides adequate internally generated erase pulses and verify sector erase w ithin the proper cell margins. protected sectors of the device will not be erased, even if they are selected with the sector erase command.
bright bm29f400t/bm29f400b m icroelec tronics inc. - 10 - multiple sectors can be erased simultaneously by writing the sixth bus cycle command of the sector erase command for each sector to be erased. the time between initiation of the next sector erase command must be less than 80 m s to guarantee acceptance of the command by the internal state machine. the time - out window can be monitored via the write operation status pin dq 3 (refer to the write operation status section for sector erase timer operation). it is recommended that cpu interrupts be disabled during this time to ensure that the subsequent sector erase commands can be initiated within the 100 m s window. the interrup ts can be re - enabled after the last sector erase command is written. as mentioned above, an internal device timer will initiate the sector erase operation 100 m s 20% (80 m s to 120 m s) from the rising edge of the last we pulse. sector erase timer write operation status pin (dq3) can be used to monitor time out window. if another falling edge of the we occurs within the 100 ms time - out window, the internal device timer is reset. loading the sector erase buffer may be done in any sequence and with any number of sectors. any command other than sector erase or erase suspend during this period and afterwards will reset the device to read mode, ignoring the previous command string. resetting the device w ith a hardware reset after it has begun execution of a sector erase operation will result in the data in the operated sectors being undefined and may be unrecoverable. in this case, restart the sector erase operation on those sectors and attempt to allow them to complete the erase operation. command definitions device operations are selected by writing specific address and data sequences in to the command register. writing incorrect addresses and data values or w riting them in the improper sequence will reset the device to read mode. table 5 defines the valid register command sequences. either of the two read/reset commands will reset the device (when applicable). during sector erase operation, data bit dq7 shows a logical "0". this operation is known as data polling. sector erase operation is complete when data on dq7 is a logical "1" (see write operation status section) at which time the device returns to rea d mode. at this time, the address pins are no longer latched. note that data polling must be performed at a sector address within any of the sectors being erased and not a protected sector to ensure that dq7 returns a logical "1" upon co mpletion of the sector erase operation. figure 2 illustrates the sector erase algorithm using typical command strings and bus operations. during execution of the sector erase command, only the erase suspend and erase resume commands are allowed. all other commands will reset the device to read mode. note: do not attempt to write an invalid command sequence during the sector erase operation. doing so will terminate the sector erase operation and the device will /reset to the read mode.
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 11 - revision a2 t able 6. command definitions command sequence bus write cycles first bus write cycle second bus write cycle third bus write cycle fourth bus write cycle fifth bus write cycle sixth bus write cycle reset/read required addr. data addr. data addr. data addr. data addr. data addr. data reset/read 1 xxxxh f0h reset word 4 5555h aah 2aaah 55h 5555h f0h ra rd /read byte aaaah 5555h aaaah electronic word 4 5555h aah 2aaah 55h 5555h 90h 01h (7) 2223h (t device id) 22abh (b device id) id byte aaaah 5555h aaaah 23h (t device id) abh (b device id) program word 4 5555h aah 2aaah 55h 5555h a0h pa pd byte aaaah 5555h aaaah chip word 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h erase byte aaaah 5555h aaaah aaaah 5555h aaaah sector word 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa 30h erase byte aaaah 5555h aaaah aaaah 5555h erase word 1 xxxxh b0h suspend byte erase word 1 xxxxh 30h re sume byte notes: 1. bus operations are defined in tables 1 and 2. 2. for a command sequence, address bit a15 = x = don't care for all address commands except for program address (pa) and sector address (sa). 3. ra = address of the memory loc ation to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. pd = data to be programmed at location pa. dat a is latched on the rising edge of we . sa = address of sector to be erased. (see table 4 for top boot and table 5 for bottom boot.) 4. the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase opera tion is in progress. 5. reading from, and programming to, non - erasing sectors is allowed in the erase suspend mode. 6. the system should generate the following address patterns: word mode: 5555h or 2aaah to addresses a0 - a14. byte mode: aaaah or 5555h to addresses a - 1 - a14. 7. address 00h returns the manufacturer's id code (bright microelectronics - adh), address 01h returns the device id code. erase suspend/erase resume commands the erase suspend command allows t he user to interrupt a sector erase operation and read data from or to a sector that is not being erased. the erase suspend command is applicable only during sector erase operation, including, but not limited to, sector erase time - out period after any sect or erase commands (30h) have been initiated.
bright bm29f400t/bm29f400b m icroelec tronics inc. - 12 - writing the erase suspend command during the time - out will result in immediate termination of the time - out period. any subsequent writes of the sector erase command will be taken as the erase resume command (30 h). note that any other commands during the time - out will reset the device to the read mode. the address pins are "don't cares" when writing the erase suspend or erase resume commands. when the erase suspend command is written during a sector erase operation, the chip will take between 1 m s and 230 m s to suspend the erase operation and go into erase suspended mode. during this time, the system can monitor the data polling or toggle bit write operation status flags to d etermine when the device has entered erase suspend mode (see write operation status section.) the system must use an address of an erasing sector to monitor data polling or toggle bit to determine if the sector erase operation has been s uspended. in erase suspend mode, the system can read data from any sector that is not being erased. a read from a sector being erased will result in write operation status data. after the system writes the erase suspend command and waits until the toggle bit stops toggling, data reads from the device may then be performed (see write operation status section). any further writes of the erase suspend command at this time will be ignored. to resume operation of sector erase, the erase resume command (30h) sho uld be written. any further writes of the erase resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed sector erase operation. dq7 data polling the bm29f400 device features data polling as a method to indicate to the host the status of the byte/word programming, chip erase, and sector erase operations. when the byte/word programming operation is in progress, an attempt to read the device will produce the compliment of the data last written to dq7. upon completion of the byte/word programming operation, an attempt to read the device will produce the true data last written to dq7. when the chip erase or sector erase operation is in progress, an attempt to read the device will produce a logical "0" at the dq7 output. upon completion of the chip erase or sector erase operation, an attempt to read the device will produce a logical "1" at the dq7 output. the flowchart for data polling (dq7) is shown in figure 3. for chip erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the data polling is valid after the last rising edge of the sector erase we pulse. for both chip erase and sector erase, data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the data polling status may not be valid. once the internal algorithm operation is close to being completed, the bm29f400 data pins (dq7) may change asynchronously while the output enable ( oe ) is asserted low. this means that the device is driving status information on dq7 at one instant and valid data at the next instant of time. depending on when the system samples the dq7 output, it may read status or valid data. even if the device has completed the internal algor ithm operation and dq7 has a valid data, data outputs on dq0 - dq6 may be still invalid. valid data on dq0 - dq7 will be read on the successive read attempts.
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 13 - revision a2 the data polling feature is only active during the byte/word programming operation , chip erase operation, sector erase operation, or sector erase time - out window (see table 7). dq6 toggle bit the bm29f400 also features the "toggle bit" as a method to indicate to the host system the status of the internal prog ramming and erase algorithms (see figure 4 for toggle bit (dq6) flowchart. during an internal programming or erase algorithm cycle, successive attempts to read ( oe toggling) data from the device will result in dq6 toggling between one and zero. once internal programming or erase operation is completed, dq6 will stop toggling and valid data will be read on the next successive attempts. during byte programming, toggle bit is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, toggle bit is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, toggle bit is valid after the last rising ed ge of the sector erase we pulse. toggle bit is also active during sector erase time - out window. in byte/word programming, if the sector being written to is protected, the toggle bit will toggle for about 300 ns and then stop toggling without the data having changed. in chip erase or sector erase, the device will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 300 ns and then dr op back into read mode, having changed none of the data. either ce or oe toggling will cause the dq6 toggle bit i to toggle. dq5 exceeded timing limits dq5 will indicate if t he byte/word programming, chip erase, or sector erase time has exceeded the specified limits (internal pulse count) of the device. under these conditions dq5 will produce a logical "1". this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the device under this condition. the oe and we pins will control the output disable functions as described in table 1. if this failure condition occurs during sector erase operation, it specifies that particular sector is bad and it may not be reused. however, other sectors are still functional and may continue to be used for the program or erase operation. the de vice must be reset to the read mode to use other sectors of the device. write the read/reset command sequence to the device, and then execute the byte/word programming or sector erase command sequence. this allows the system to continue t o use the other active sectors in the device. if this failure condition occurs during chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. in so, the chip should not be reused. if this failure condition occurs d uring byte/word programming operation, it indicates the entire sector containing that byte is bad and this sector may not be reused (other sectors are still functional and can be reused.)
bright bm29f400t/bm29f400b m icroelec tronics inc. - 14 - the dq5 failure condition may also appear if a us er tries to program a non blank location without erasing. in this case, the device may exceed time limits and not complete the internal algorithm operation. hence, the system never reads a valid data on dq7 bit and dq6 never stops toggling. once the device has exceeded timing limits, the dq5 bit will indicate a "1". dq3 sector erase timer after the completion of the initial sector erase command sequence, the sector erase time - out window will begin. dq3 will remain low un til the time - out window is closed. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit indicates the device has been written with a valid erase comma nd, dq3 maybe used to determine if the sector erase time - out window is still open. if dq3 is a logical "1", the internally controlled erase cycle has begun. attempts to write subsequent command to the device will be ignored until the erase operation is com pleted as indicated by data polling or toggle bit. if dq3 is a logical "0", the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 were high on the second status check, the command may not have been accepted. refer to table 7: write operation status flags. write operations status status dq7 dq6 dq5 dq3 in byte/word programming operation dq7 toggle 0 n/a progress chip or sector erase operation 0 toggle 0 1 erase suspend mode (non - erase suspended sector) data data data data exceeded byte/word programming operation dq7 toggle 1 0 time limits chip or sector erase operation 0 toggle 1 1 table 7. write operation status flags (1) notes: dq0, dq1, dq4 are reserve pins for future use. ry/by ready/busy status the bm29f400 provi des a ry/by open - drain output pin as a way to indicate to the host system that an internal programming or erase operation is either in progress or has been completed. if the ry/by output is low, the device is busy with either a programming or erase operati on. if the ry/by output is high, the device is ready to accept a read, programming, or erase command. when the ry/by pin is low, the device will not accept any additional programming or erase commands with the exception of the erase suspend command. if the bm29f400 is placed in an erase suspend mode, the ry/by output will be high.
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 15 - revision a2 during a programming operation, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven l ow after the rising edge of the sixth we pulse. the ry/by pin will indicate a busy condition during the reset pulse. refer to the timing waveforms for the ry/by status pin for further clarification. the ry/by pin is high in the standby mode. since this is an open - drain output, several ry/by pins can be tied together with a pull - up resistor to vcc. reset hardware reset the bm29f400 device may be reset by d riving the reset pin to v il . the reset pin must be kept low (v il ) for at least 500 ns. pulling the reset pin low will terminate any operation in progress. the internal state machine will be reset to the read mode 1 ms to 230 ms after the reset pin is driven low. if a hardware reset occurs during a programming or erase operation, the data at that particular location will be indeterminate. when the reset pin is low and the internal reset is complete, the device goes to standby mode and cannot be accessed. also, note that all the data output pins are tri - stated for the duration of the reset pulse. once the reset pin is taken high, the device requires 500 ns of wake up time until outputs are valid for a read access. the reset pin may be tied to the system reset input. therefore, if a system reset occurs during an internal programming or erase operation, the device will be automatically reset to read mode. this will enable the system's microprocessor to read the boot - up firmware from the flag's memory. data protection the bm29f400 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power - up the device automatically resets the internal stat e machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi - bus cycle command sequences. the device also incorporates several features to prevent inad vertent write cycles resulting from vcc power - up and power - down transitions or system noise. low vcc write inhibit to avoid initiation of a write cycle during vcc power - up and power - down, a write cycle is locked out for vcc less than 3.2v (typically 3.7v). if vcc < v lko , the command register is disabled and all internal programming/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until th e vcc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when vcc is above 3.2v. write pulse "glitch" protection noise pul ses of less than 5 ns (typical) on oe , ce or we will not initiate a write cycle.
bright bm29f400t/bm29f400b m icroelec tronics inc. - 16 - logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical "0" while oe is a logical "1". power - up write inhibit power - up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power - up. sector unprotect the bm29f400 also features a sector unprotect mode, so that protected sectors may be unprotected to incorporate any changes in the code. protecting all sectors is necessary bef ore unprotecting any sector(s). sector unprotection is accomplished in a prom programmer. start write program command sequence (see below) data polling device last address ? no yes programming completed program command sequence (address/command) 5555h/aah 2aaah/55h 5555h/a0h program address/ program data increment address figure 1. internal programming algorithm
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 17 - revision a2 start write erase command sequence (see below) data polling or toggle bit successfully completed erase completed chip erase command sequence (address/command) 5555h/aah 2aaah/55h 5555h/80h 5555h/aah 2aaah/55h 5555h/10h individual sector/multiple sector erase command sequence (address/command) 5555h/aah 2aaah/55h 5555h/80h 5555h/aah 2aaah/55h sector address/30h sector address/30h sector address/30h additional sector erase commands are optional figure 2. internal erase algorithm
bright bm29f400t/bm29f400b m icroelec tronics inc. - 18 - start read byte (dq0-dq7), addr = va dq7 = data yes no dq5 = 1 no yes read byte (dq0-dq7), addr = va dq7 = data fail pass yes va = byte address for programming = any of the sector addresses within the secotr being erased during sector erase operation. = xxxxh during chip erase figure 3. data polling algorithm notes: dq7 is rechecked even if dq5 = logical "1" because dq7 may change simultaneously with dq5.
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 19 - revision a2 start read byte(dq0-dq7) addr = don't care dq6 = toggle no dq5 = 1 ? yes yes fail pass yes read byte (dq0-dq7) addr = don't care dq6 = toggle ? no no figure 4. toggle bit algorithm note: dq6 is rechecked even if dq5 = logical "1" because dq6 may stop toggling at the sam e time as dq5 changing to a logical "1". absolute maximum ratings parameter rating unit storage temperature plastic packages - 65 to +125 c ambient temperature with power applied - 55 to +125 c voltages with respect to ground all pins except a9 (note 1 ) vcc (note 1); a9 (note 2) - 2 to +7 - 2 to +7 - 2 to +14 v output short circuit current (note 4) 200 ma notes : 1. minimum dc voltage on input or i/o pins is - 0.5v. during voltage transitions, inputs may overshoot vss to - 2.0v for periods of up to 20 ns. maximum dc voltage on output and i/o pins is vcc +0.5v. during voltage transitions, outputs may overshoot to vcc +2.0v for periods up to 20 ns. 2. minimum dc input voltage on a9 pin is - 0.5v. during voltage transitions, a9 may overshoot vss to - 2.0v for periods of up to 20 ns. maximum dc input voltage on a9 is +12.5v which may overshoot to 14.0v for periods of up to 20 ns. 3. no more than one output shorted at a time. duration of the short circuit should not be greater than one second.
bright bm29f400t/bm29f400b m icroelec tronics inc. - 20 - operating rang es parameter rating unit commercial (c) devices 0 to +70 c extended (i) devices - 55 to +125 c vcc supply voltage vcc for bm29f400 - 90 +4.5 to 5.5 v note : operating ranges define those limits between which the functionality of the device is guaranteed. *notice : stresses above those listed under 2 absolute maximum ratings 2 may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sec tions of this specification is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. -2.0 v -0.5 v +0.8 v 20 ns 20 ns 20 ns figure 5. vcc + 2.0 v vcc + 0.5 v 2.0 v 20 ns 20 ns 20 ns figure 6. maximum negative overshoot waveform maximum positive overshoot waveform
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 21 - revision a2 dc characteristics ttl/nmos compatible parameter sym. test conditions min. max. unit input load current i li v in = vss to v cc , v cc = v cc max. 1.0 m a a9 input load current i lit v cc = v cc max., a9 = 12.5 v 1.0 m a output leakage current i lo v out = vss to v cc , v cc = v cc max. 1.0 m a v cc active current (1) i cc1 ce = v il , oe = v ih byte 40 ma word 50 ma v cc active current (2,3) i cc2 ce = v il , oe = v ih 60 ma v cc standby current i cc3 v cc = v cc max., ce = reset = v ih 1.0 ma v cc standby current ( reset ) i cc4 v cc = v cc max., reset = v il 1.0 ma input low level v il - 0.5 0.8 v input high level v ih 2.0 v cc +0.5 v voltage for electronic v id v cc = 5.0v 11.5 12.5 v output low voltage v ol i ol = 5.8 ma, v cc = v cc min. 0.45 v output high voltage v oh i oh = - 2.5 ma, v cc = v cc min. 2.4 v notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent com ponent (at 6 mhz). the frequency component typically is less than 2 ma/mhz, with oe at v ih . 2. i cc active while internal algorithm (program or erase) is in progress. 3. not 100% tested.
bright bm29f400t/bm29f400b m icroelec tronics inc. - 22 - dc characteristics, continued cmos compatible parameter sym. test conditions min. max. unit input load current i li v in = v ss to v cc , v cc = v cc max. 1.0 m a a9 input load current i lit v cc = v cc max., a9 = 12.5 v 1.0 m a output leakage curre nt i lo v out = v ss to v cc , v cc = v cc max. 1.0 m a v cc active current (1) i cc1 ce = v il , oe = v ih byte 40 ma word 50 ma v cc active current (2,3) i cc2 ce = v il , oe = v ih 60 ma v cc standby current i cc3 v cc = v cc max., ce = v cc 0.5v, reset = v cc 0.5v 100 m a vcc standby current ( reset ) i cc4 v cc = v cc max., reset = v ss 0.5v 100 m a input low level v il - 0.5 0.8 v input high level v ih 0.7 v cc v cc +0.3 v voltage for electronic id and sector protect v id v cc = 5.0 v 11.5 12.5 v output low voltage v ol i ol = 5.8 ma, v cc = v cc min. 0.45 v output high voltage v oh1 i oh = - 2.5 ma, v cc = v cc min . 0.85 v ih v v oh2 i oh = - 100 ma, v cc = v cc min. v cc - 0.4 v low v cc lock - out voltage v lko 3.2 4.2 v notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component t ypically is less than 2 ma/mhz, with oe at v ih . 2. i cc active while internal algorithm (program or erase) is in progress. 3. not 100% tested.
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 23 - revision a2 ac characteristics read - only operations parameter sym. description test setup - 90 - 120 - 150 unit jedec standard t avav t rc read cycle time (2) min. 90 120 150 ns t avqv t acc address to output delay ce = v il oe = v il max. 90 120 150 ns t elqv t ce chip enable to output delay oe = v il max. 90 120 150 ns t glqv t oe output enable to output delay max. 35 50 55 ns t ehqz t hz chip enable to output high z (3,4) max. 20 30 35 ns t ghqz t df output enable to output high z (2,3) 20 30 35 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min. 0 0 0 ns t ready reset pin low to read mode (4) max. 20 20 20 ms t elfl t elfh ce to byte switching low or high max. 5 5 5 ns notes: 1. test conditions: output load: 1 ttl gate and 100 pf input rise and fall times: 20 ns; input pulse levels: 0v to 3 v 2. timing measurement reference level input/output: 1.5v 3. ou tput driver disable time. 4. not 100% tested. device under test c l 6.2 kohm in3064 or equivalent 2.7 kohm diodes = in3064 or equivalent 5.0 v figure 7. test condition note: cl = 100 pf including jig capacitance.
bright bm29f400t/bm29f400b m icroelec tronics inc. - 24 - ac characteristics programming/erase operations parameter sym. description - 90 - 120 - 150 unit jedec standard t avav t wc write cycle time (1) min. 90 120 150 ns t avwl t as address setup time min. 0 0 0 ns t wlax t ah address hold time min. 45 50 50 ns t dvwh t ds data setup time min. 45 50 50 ns t whdx t dh data hold time min. 0 0 0 ns t oes output enable setup time m in. 0 0 0 ns t oeh output enable read (1) min. 0 0 0 ns hold time toggle & data polling (1) min. 10 10 10 ns t ghwl t ghwl read recover time before write min. 0 0 0 ns t elwl t cs ce setup time min. 0 0 0 ns t wheh t ch ce hold time min. 0 0 0 ns t wlwh t wp write pulse width min. 45 50 50 ns t whwl t wph write pulse width high min. 20 20 20 ns t whwh1 t whwh1 byte programming operation typ. max. 16 400 16 400 16 400 m s m s t whwh2 t whwh2 sector erase operation (2) typ. max. 0.26 12 0.26 12 0.26 12 sec t whwh3 t whwh3 chip erase operation (2) typ. max. 2.0 90 2.0 90 2.0 90 sec t vcs vcc setup time (1) min. 50 50 50 ms t vidr rise time to v id (1,3) min. 500 500 500 ns t oesp oe setup t ime to we active (1, 3, 4) min. 4 4 4 ms t rp reset pulse width min. 500 500 500 ns t rsp reset setup time ( 3) min. 4 4 4 m s t busy programming/erase valid to ry/by delay (1) min. 40 50 60 ns t vlh t voltage transition time (1, 4) min. 4 4 4 ms t wpp1 sector protect write pulse width (4) min. 100 100 100 ms t wpp2 sector unprotect write pulse width (4) min. 350 350 350 ms t csp ce setup time to we active (1, 4 ) min. 4 4 4 ns notes: 1. not 100% tested. 2. does not include pre - programming time. 3. this timing is for temporary sector unprotect operation. these timings are for sector protect and/or sector unprotect operations.
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 25 - revision a2 switching waveforms waveform input output must be steady will be steady may change from h to l will be change from h to l may change from l to h will be change from l to h don't care, any change permitted change, state unknown does not apply center line is high impedance off state address ce oe we outputs address stable high z t rc t acc t oe t oeh t ce t oh t df t hz high z output vaild figure 8. ac waveforms for read operations
bright bm29f400t/bm29f400b m icroelec tronics inc. - 26 - switching waveforms, continued address ce oe we data t wc 5555h pa pa data polling a0h pd dq7 d t ah t as t ghwl t wp t wph t cs t ds t whwh1 t dh out 5.0v gnd v cc figure 9. ac waveforms program operations notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programme d at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. 6. these waveforms are for 16 - bit mode. address ce oe we data 5.0v gnd v cc t vcs t ds t dh t cs t wph t wp t ghwl t as t ah 5555h 5555h 2aaah 5555h 2aaah sa aah 55h 80h aah 55h 10h/30h figure 10. ac waveforms chip/sector erase operations notes: 1. sa is the sector address for sector erase. address = x = don't care for chip erase. 2. these waveforms are for 16 - bit mode.
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 27 - revision a2 switchi ng waveforms, continued ce oe we data 5.0v gnd v cc t ch t oe t df t oh t oeh t ce t whwh 1 or 2 t oe high z dq0-dq7 valid data dq0-dq6=invalid dq7 dq7=valid data dq0-dq6 dq7 figure 11. ac waveforms for data polling during internal algorithm operations note: dq7 = valid data (the device has completed the internal program or erase operation.) ce oe we data 5.0v gnd v cc data (dq0-dq7) dq6=toggle dq6=toggle dq6= stop toggling dq0-dq7 valid t oe t oes t oeh figure 12 ac waveforms for toggle bit during internal algorithm operation note: dq6 stops toggling (the device has completed the internal program or erase operation.)
bright bm29f400t/bm29f400b m icroelec tronics inc. - 28 - switching waveforms, continued ce we by/ry 5.0v vcc gnd entire programming or erase operations the rising edge of the last we signal t busy figure 13. ry/by timing diagram during pro gram/erase operation ry/by reset data 5.0v gnd vcc ready rp t pwh vaild data figure 14. reset timing diagram
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 29 - revision a2 switching waveforms, continued address ce oe byte data (dq0-dq7) data (dq8-dq14) dq15/a-1 address stable data output on dq0-dq7 data output on dq0-dq7 data outputon dq8-dq14 data outputon dq15 address input high z high z high z t wc t avfl t elfl t df t oe t ce t acc t flqz t acc t oh high z figure 15. byte timing diagram for read operation the falling edge of the last we signal t set t as ( ) t hold t ah ( ) ce we byte figure 16. byte timing diagram for write operation
bright bm29f400t/bm29f400b m icroelec tronics inc. - 30 - start reset = v (note 1) perform erase or program operations reset = v temporary sector unprotect completed (note 2) id ih figure 17. temporary sector unprotect algorithm notes: 1. all protected sector groups unprotected. 2. all previously protected sector groups are protected again. 5v t vidr program or erase command sequence reset 12v ce we ry/by t rsp figure 18. temporary unprotect timing diagram
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 31 - revision a2 ac characteristics programming/erase operations parameter sym. description jedec standard - 90 - 120 - 150 unit t avav t wc write cycle time (1) min. 90 120 150 ns t av el t as address setup time min. 0 0 0 ns t elax t ah address hold time min. 45 50 50 ns t dveh t ds data setup time min. 45 50 50 ns t ehdx t dh data hold time min. 0 0 0 ns t oes output enable setup time (1) min. 0 0 0 ns t oeh output enable read (1) min. 0 0 0 ns hold time toggle and data polling (1) min. 10 10 10 ns t ghwl t ghwl read recover time before write min. 0 0 0 ns t wlel t ws we setup time min. 0 0 0 ns t ehwh t wh we hold time min. 0 0 0 ns t eleh t cp ce pulse width min. 45 50 50 ns t ehel t cph ce pulse width high min. 20 20 20 ns t whwh1 t whwh1 byte programming operation typ. 16 16 16 ms max. 400 400 400 ms t whwh2 t whwh2 sector erase operation (2) typ. 0.26 0.26 0.26 sec max. 12 12 12 sec t whwh3 t whwh3 chip erase operation (2) typ. 2.0 2.0 2.0 sec max. 90 90 90 sec t vcs vcc setup time (1,3) min. 50 50 50 ms t vidr rise time to v id (1,3) min. 500 500 500 ns t vlht voltage tra nsition time (1,3) min. 4 4 4 ms t wpp1 sector protect write pulse width (4) min. 100 100 100 ms t wpp2 sector unprotect write pulse width (4) min. 10 10 10 ms t oesp oe setup time to we active (1, 3) min. 4 4 4 ms t csp oe setup time to we active (1, 4) min. 4 4 4 ns notes : 1. not 100% tested. 2. does not include pre - programming time. 3. this timing is for sector unprotect operation. 4. output driver disable time.
bright bm29f400t/bm29f400b m icroelec tronics inc. - 32 - switching wa veforms, continued wc t ah t as t ghwl t wp t whwh1 t cs t wph t d h t ds t 5555h pa pa data polling d dq7 pd a0h address ce oe we data 5.0v vcc gnd out figure 19. alternate ce controlled program operation timings notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. 6. these waveforms are for the x16 mod e.
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 33 - revision a2 erase and programming performance parameter limits min. typ. max. unit sector erase time 0.33 15 sec chip erase time 2.4 120 sec byte programming time 16 400 m s chip programming time 8 200 sec erase/program cycles 10,000 100,000 cycles l atch up characteristics parameter min. max. input voltage with respect to vss on all i/o pins - 1.0v vcc + 1.0v vcc current - 100 ma + 100 ma note: includes all pins except vcc. test conditions: vcc = 5.0v, one pin at a time . capacitance tsop pin parameter symbol test setup typ. max. unit input capacitance c in v in = 0 6 7.5 pf output capacitance c out v out = 0 8.5 12 pf control pin capacitance c in2 v in = 0 8 10 pf notes: 1. sampled, not 100% test ed. 2. test conditions t a = 25 , f = 1.0 mhz. data retention parameter test conditions min. unit minimum pattern data retention time 150 10 years minimum pattern data retention time 125 20 years
bright bm29f400t/bm29f400b m icroelec tronics inc. - 34 - ordering information part no. acc ess time ( n s) power supply current max. ( m a) boot block package cycling (min.) temperature range 29f400t - 90tc 29f400t - 12tc 29f400b - 90tc 29f400b - 12tc 90 120 90 120 60 60 60 60 top top bottom bottom 48 - pin tsop 48 - pin tsop 48 - pin tsop 48 - pin tsop 1 0,000 10,000 10,000 10,000 0 c - 70 c 0 c - 70 c 0 c - 70 c 0 c - 70 c notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intend ed for use in applications where personal injury might occur as a consequence of product failure. 3. typical program/erase cycle is 100,000.
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 35 - revision a2 appendix a: compatibility to amd's amd29f400b: the device is essentially fully functional compatible to the amd 29f400b except for three issues: 1. during erase suspend 2. dq2 status flag 3. command address subset during erase suspend, the device can only read data in the memory -- not program or execute an auto command like the amd29400b. also, the dq2 flag is not available. this flag is used to determine during multiple or single sector erase whether a sector has been selected for erase. dq2 can only be used during and embedded sector erase operation or during erase suspend. in the amd device, commands do not req uire address pin a15, a14, a13, a12, a11 to be forced during the command sequence. this makes their device slighly easier to inadvertently create a command and cause a program, erase or malfunction. the advantage of reducing the address to a subset is to s implify the hardware interface in systems where control signals are limited in number. the 29f400b reduces the interface requirement by 4 signals. however if the full address is supplied (i.e.2aaah and 5555h) by the host system, there will be no incompatib ility using either device.
bright bm29f400t/bm29f400b m icroelec tronics inc. - 36 - package dimensions tsop48 48 - pin standard thin small outline package (measured in millimeters) 1 48 24 pin 1 i.d. 18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21 .050 .070 0 5 1.20 max 0.25mm(0.0098)bsc 25 11.90 12.10 0.05 0.15 0.95 1.05 0.50 bsc
bright bm29f400t/bm29f400b m icroelectronics inc. a winbond company publication release date: december 1999 - 37 - revision a2 version history version date page description a1 may 1999 - initial issued a2 dec. 1999 1, 3, 34, 35, 37 remov e psop package 21, 35 remove industrial specifications 23 change ac testing input level from 0.45v/2.4v to 0v/3v and input/output reference level to 1.5v headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5796096 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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